1. Field of the Invention
The present invention relates to branch prediction of central processing units (CPUs), and more particularly, to branch prediction methods and devices capable of predicting a first taken branch instruction within a plurality of fetched instructions.
2. Description of the Prior Art
FIG. 1 illustrates a branch prediction mechanism 100 utilized in a conventional single-issue processor that fetches only one instruction per clock cycle, where a portion of a program counter (PC) PC0 is utilized for indexing an entry in a branch target buffer (BTB) 110, so a branch predictor 120 performs branch prediction according to the entry's elements Tag0, Hist0, and TA0 outputted from the BTB 110, in order to predict the next PC.
FIG. 2 illustrates a branch prediction mechanism 200 utilized in a conventional multi-issue processor that fetches multiple instructions per clock cycle, where a portion of each PC (e.g. PC0, PC1, PC2, and PC3) is utilized for indexing an entry in a BTB 210. In the combinational module 220 shown in FIG. 2, four comparison and directional prediction circuits (CDPCs) 222-0, 222-1, 222-2, and 222-3, which are four copies of a set of comparator 122 and direction predictor 124, are required for performing branch prediction according to four sets of elements (Tag0, Hist0, TA0), (Tag1, Hist1, TA1), (Tag2, Hist2, TA2), and (Tag3, Hist3, TA3) of four entries corresponding to the PCs PC0, PC1, PC2, and PC3, respectively. In addition, complicated architecture such as a logic circuit 226 and a control circuit (not shown) of the BTB 210 should be properly designed to predict a first taken branch instruction, so as to predict the next PC. As a result, material and design costs of the branch prediction mechanism 200 are significantly high, and the overall chip area required for implementing the multi-issue processor is quite large.